1. Field of the Invention
The present invention relates to recording and reproducing digital data, and more particularly to a method and apparatus for converting data received in a random rate to a fixed rate.
2. Discussion of the Related Art
Digital broadcastings by which programs are transmitted in digital signals using digital compression technologies, have been in, or will be put into commercial use in the U.S.A., Europe, and Asia in the forms of satellite broadcastings, cable broadcastings, and terrestrial broadcastings. Because the digital broadcasting provides entertainment as well as a variety of multimedia services, the digital broadcasting receives close attention as the broadcasting method of the next veneration.
Following this trend, demands on the commercial production of Digital Video Cassette Recorder (DVCR) which records/reproduces a digital broadcasting program in a digital signal are also increased. However, the standard for a DVCR is a VCR format which receives a program selected by an external digital TV in an MPEG 2 transport packet data, and merely records the bitstream before reproducing the bitstream. Thus, an interface is required for a data transmission between a digital VCR of the DVCR standard and a digital TV. In the data of the aforementioned MPEG 2 transport packet data, a control command between the two devices are time-division multiplexed. Moreover, the DVCR records/reproduces the data at a fixed rate to maintain stabilization of the system.
Although the MPEG2 transport packet data of a program selected by a digital TV is recorded at a fixed rate, the data may be received in burst, in a variable rate like the Echostar satellite broadcasting of the U.S.A. A broadcasting data is transmitted at a variable transmission rate depending on a program characteristic. For efficient use of a channel, motions or sports require a real time compression and are transmitted at a rate of approximately 6 Mbps, while dramas with less motion can be greatly compressed and are transmitted at a lower rate of approximately 4 Mbps. Accordingly, a smoothing buffer is required to convert the data received in a variable rate into a fixed rate. On the other hand, a desmoothing buffer is required to reproduce the burst of time intervals to satisfy an MPEG 2 time jitter limitation. Thus, a smoothing buffer is used in the recording stage and a desmoothing buffer is used in the reproduction stage. A size of the buffer is determined by the maximum recordable variable bit rate.
FIG. 1 illustrates a block diagram of a digital TV and a DVCR in the related art, wherein a tuner 12 in a digital TV 10 selects one channel from a plurality of channels received through an antenna 11 and demodulates the received signal; and a de-MUX/program selector 13 selects one desired program from a plurality of programs included in the channel. If a viewer selects a particular program for viewing, the selected program is output to the MPEG decoder 14 wherein the video and audio of the selected program is restored. If a recording is desired, the selected program is output as an MPEG transport packet to a digital interfacer D-IF 21 in the DVCR 20 through the digital interfacer D-IF 15.
As shown in FIG. 2(a), the transport packets of the channel tuned by the tuner 12 are mixed with the transport packets of various other programs. Thus, when the de-Mux/program selector 13 selects one program, only the transport packets of the selected program is selected as shown in FIG. 2(b). Accordingly, only the selected packets as shown in FIG. 2(c) are output to the MPEG decoder 14 or the D-IF.
The DVCR further includes a time stamp generator 22 counting the point of time upon receiving the MPEG 2 transport packets through the D-IF 21 with respect to a reference clock (i.e., 27 MHz clock) as shown in FIG. 2d, and generating time stamps as shown in FIG. 2(e); a smooth buffer 23 storing the MPEG 2 transport packet data received through the D-IF 21 together with the time stamp signal generated in the time stamp generator 22. A memory controller 24 controls the reading/writing timings of the shuffle memory 25 and reads the data from the smooth buffer 23 to store the read data in the shuffle memory 25 as shown in FIG. 2(f).
Also shown in FIG. 2(f), a null data is inserted if there is no data from the digital TV while the memory controller 24 generates a read signal. By inserting a null data, the transport packets are recorded at a fixed rate as shown in FIG. 2(c), even if the transport packets are not received at a fixed rate.
The time stamp signal is stored in the shuffle memory 25 together with the transport packets because the amount of transport packets received by the smooth buffer 23 may be greater than the amount of transport packet read from the smooth buffer 23 by the memory controller 24. When the transport packets are stored in the shuffle memory 25, the difference in the amount of transport packets can shift the time frame by which the packets are stored. Thus, storing both the time stamp signal and the transport packets prevents a time shift in storing the transport packets in the shuffle memory. Moreover, the dual storage also satisfies the timing jitter at the reproduction.
The data stored in the shuffle memory 25 contains an outer code word and an inner code word which are processed for an error coding correction (ECC). Particularly, the outer code word is first inputted to an ECC 26 through the memory controller 24 and stored back in the shuffle memory 25 after being incorporated into the ECC timing. Similarly, the inner code is then inputted to the ECC 26 and stored back in the shuffle memory 25 after being incorporated into the ECC timing. The fully incorporated outer and inner codes are read again from the shuffle memory 25 through the memory controller 24 and output to a synchronization/ID adder 27 wherein a synchronization (sync) signal and an ID are added to the codes. From the sync/ID adder 27, the codes are arranged into a synchronous block of a DVCR recording format and output to a Non-Return-to Zero (NRZI) 28. The NRZI 28 is a demodulator adapted to invert the data with a `1` signal and inverts the status of any data with a `1` signal. An NRZI modulated signal is amplified by a recording amplifier 29 and recorded on a tape 30.
The data input/output between the smooth buffer 23 and the shuffle memory 25 will be explained in detail with reference to FIG. 3. The shuffle memory 25 has a bank0 and a bank1, each bank functioning alternatively as a part of one block for ECC. When the bank0 is under an inner error correction, the bank1 is under an outer error correction, and vice versa. Specifically, the outer code word `c` stored in the shuffle memory 25 is output to an outer ECC 26-2 within the ECC 26 for an outer error correction. Once the outer code is incorporated in the ECC 26-2, the incorporated data `d` is output and stored back in an appropriate location of the shuffle memory 25 under the control of the memory controller 24.
Upon completion of the outer error correction, the inner code word `e` is output to an inner ECC 26-1 within the ECC 26 for an inner ECC. However, since the inner code word `e` is output to the inner ECC 26-1 after the completion of the outer ECC, when the inner code is incorporated in the ECC 26-1, the incorporated data `f` is ready to be recorded on a tape. Thus, it is unnecessary to store the data `f` back in the shuffle memory 25. Accordingly, under the control of the memory controller 24, the data output by the smooth buffer 23 is stored in the region of the shuffle memory 25 from which the inner code word had been output.
For example, as shown in FIG. 3, when the bank1 carries out the outer ECC, the bank0 carries out the inner ECC. When the bank0 outputs an inner code word `e` to the inner ECC, a data `b` from the smooth buffer 23 is stored in the location from which the inner code word has been output. Once the inner code word is output to the ECC 26-2, the bank0 stores only a null data together with the data from the smooth buffer 23. Hence, the bank0 outputs the outer code of the data received from the smooth buffer 23 to the ECC 26-2 for outer ECC and stores back the outer code incorporated data in the appropriate memory location. Similarly, when the bank1 carries out the inner ECC after the completion of the outer ECC, the data from the smooth buffer 23 is stored in bank1 into the location from which the inner code word has been output. Because the inner ECC `e`, the storage of the data `b` from the smooth buffer 23, and the outer ECC `c` and `d` are successively processed by the shuffle memory 25 within a time period of T, as shown in FIG. 4, a parallel clock is adequate.
The discussion thus far has been the recording of the data, but the reproduction process is carried out according to a process opposite to the aforementioned recording process. The signal reproduced from the tape 30 is amplified in the amplifier 31, decoded in an INRZI 32, and the sync signal and ID is detected by a sync/ID detector 33. The synchronous blocks detected by an sync/ID detector 33 is stored in the shuffle memory 36 through an memory controller 35; processed for an inner an outer ECC through an ECC 34; and timely output through a memory controller 35 to a desmooth buffer 37 and to a time stamp generator 38, as shown in FIG. 2(g).
The time stamp generator 38 separates the time stamp signals from the received data for a comparison with respect to a reproduction reference clock (i.e. 27 Mhz) as shown in FIG. 2(h). By the comparison, the transport packets are detected at the exact time points within the data from the desmooth buffer 37, as shown in FIG. 2(j). The detected transport packets are output to the digital TV through the D-IF 21. During the reproduction process, the null data inserted in the recording process is removed by skipping the data. Thus, the MPEG 2 transport packets are received/forwarded with the same timing in the recording/reproduction, thereby satisfying the limitation on the MPEG 2 timing jitter.
As discussed above, the size of the buffer is determined by the maximum recordable variable bit rate. Particularly, a theoretical size of a buffer for the smoothing and desmoothing process can be calculated as follows.
Assuming that no overflow occurs from a buffer with reference to one track, and if one track time (Top)=1/60 sec, a recording rate (Rrec)=13.80 bps, an input rate (Rtransmit)=30 Mbps, a maximum relative delay Td can be expressed and calculated with equation (1) below. ##EQU1##
Also, a minimum smoothing buffer size Bsmooth can be expressed and calculated with the following equation (2). ##EQU2##
For 81 TS packets, a smoothing buffer size of approximately 15 Kbytes is required. By employing an exclusive buffer of the aforementioned size for smoothing and desmoothing, which is separate from the main storage memory (the shuffle memory), the related art has problems of high production costs and the instability in the system operation. Also, because the memory size is calculated with the minimal requirements, the size of the actual memory is often greater than the calculated maximum storage size. For example, if the main storage memory requires a maximum storage capacity of 2.1 Mbytes, a memory of 4 Mbytes must be selected, thereby severely wasting 1.9 Mbytes of memory.